Field of the Invention
The present invention relates to processes capable of forming microelectronic structures having small features (≤20 nm) using freestanding T-shaped template structures.
Description of Related Art
As features shrink to meet the demands of more efficient device performance, improved materials and processes are needed. The most common form of improvement over the decades has been reducing the wavelength of radiation (e.g., g-line at 436 nm, i-line at 365 nm, KrF at 248 nm, and ArF at 193 nm) used for patterning to improve resolution according to the Rayleigh criteria. In some cases, smaller features can be printed, but the pitch of these features is large due to contrast limitations. The next step in wavelength reduction is extreme ultraviolet (EUV) lithography at 13.5 nm, which progresses into the x-ray range of optics and thus brings a host of problems, including cost.
Multiple patterning processes have also been proposed for feature size reduction. Multi-patterning technology usually takes the form of repeating lithography and etch processes. For example, it is typically a lithography-etch-lithography-etch process for double patterning, and lithography-etch-lithography-etch-lithography-etch for triple patterning. However, double patterning has a serious issue of overlay and alignment, which prevents this technology from being used to fabricate dense lines (line:space=1:1). Triple patterning compounds this issue, as it involves two lithography steps that require alignment.
To address the issue of overlay, the CVD spacer process, which involves CVD underlayer-lithography-etch-CVD conformal film-etch, was developed to eliminate the second lithography step. This technology has been successfully used in mass production of dense lines with 32 nm and 28 nm, and has been extended to CVD underlayer-lithography-etch-CVD conformal film-etch-CVD conformal film-etch triple patterning. However, this scheme contains numerous CVD and etch steps, which result in not only high cost but also many technical challenges due to the accumulation of process errors for each step.
To address the cost and technical difficulties of the spacer process, some modified methods have been proposed to reduce the number of steps. For example, the photoresist pattern could be directly used as the template for a conformal film to prepare underlayers, eliminating the initial CVD steps, along with using a post-lithography etch to prepare the template. The conformal coating can be applied on the photoresist template by a CVD process. However, the feasibility of this process is still under question, because a CVD process is always performed at a high temperature, which can damage the photoresist pattern. To address the issue of the difficulty of a CVD process, a spin-on process at a low temperature has been developed, and can be extended to triple patterning as lithography-etch-lithography-spin-on conformal film-etch. But this triple-patterning process has two lithography steps and still has the issue of overlay.
Thus, there remains a need in the art for technology that allows current ArF lithography techniques to be used to create features that typically could only be patterned using an EUV light source. Advantageously, this would eliminate the capital outlay for an EUV tool, save a tremendous amount of money for the manufacturer, and allow existing logistics and materials to be used, saving even more money and resources.